EDN

FPGA-to-ASIC conversion a crucial concern

It is clear that FPGAs are great for prototyping and low-volume production. It's also clear, however, that any relatively complex mid- to high-volume design for which power consumption, component cost ...
EDN

Virtually every ASIC ends up an FPGA

Over the past decade, designers around the world have argued over the relative merits of using ASICs or FPGAs to implement digital electronic designs. This ongoing discussion has typically positioned ...
Embedded

Moving from FPGA to ASIC for your AI chip? Here’s what you should know

Perhaps you are designing an embedded inference engine for edge computing. Or you are taking the next step in automotive vision processing. Or maybe you have an insight that can challenge Nvidia and ...
AV Network

Justin Kennington on AV Supply Chain Using FPGA vs. ASIC Chips

SDVoE Alliance President, Justin Kennington shares his perspective on how FPGA versus ASIC chips impacts the product supply chain in the AV industry. When you purchase through links on our site, we ...
Hackaday

Your Own Open Source ASIC: SkyWater-PDK Plans First 130 Nm Wafer In 2020

You might have caught Maya Posch’s article about the first open-source ASIC tools from Google and SkyWater Technology. It envisions increased access to make custom chips — Application Specific ...
Digi Times

FPGA vs ASIC: Altera CEO highlights FPGA's advantage in AI era

Embedded World 2025 officially commenced this week in Nuremberg, Germany, with Sandra Rivera, CEO of FPGA company Altera, delivering the keynote address. In her presentation, Rivera discussed key ...
Business Wire

MathWorks Speeds FPGA and ASIC Verification with Universal Verification Methodology (UVM) Support

NATICK, Mass.--(BUSINESS WIRE)--MathWorks today announced that HDL Verifier provides support for the Universal Verification Methodology (UVM) starting with Release 2019b, which is currently available.
Business Wire

BitHull Overtakes ASIC Market with New FPGA Miners

COPENHAGEN, Denmark--(BUSINESS WIRE)--BitHull S.A. ( www.BitHull.com) is pleased to announce the launch of its two new crypto miners BH Miner and BH Miners Box. These miners have been built around ...
Design News

Is Platypus from Zero ASIC the FPGA equivalent to RISC-V?

Before I tell you what I’m about to tell you, let’s first refresh our minds as to RISC-V processors. Why? Well, because even though what I’m about to tell you has nothing to do with RISC-V per se, in ...
Queen Mary University of London

Neuromorphic Healthcare Monitoring on FPGA/ASIC

This PhD will develop a spiking neural network (SNN)–based accelerator for real-time, on-device Electrocardiography (ECG) classification in wearable health monitors. The work spans algorithms à ...
VentureBeat

FPGA chips are coming on fast in the race to accelerate AI

AI is hungry, hyperscale AI ravenous. Both can devour processing, electricity, algorithms, and programming schedules. As AI models rapidly get larger and more complex (an estimated 10x a year), a ...